Y. Mitsuyama, T. Asada, and M. Eguchi, “Measurement of Variations in FPGAs under Various Load Conditions,” IPSJ Transaction on System LSI Design Methodology, Vol. 13, pp. 39-31, Feb. 2020.
H. Ochi, K. Yamaguchi, T. Fujimoto, J. Hotate, T. Kishimoto, T. Higashi, T. Imagawa, R. Doi, M. Tada, T. Sugibayashi, W. Takahashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, J. Yu, and M. Hashimoto, “Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture with Overlay Via-Switch Crossbars,” IEEE Transactions on VLSI Systems, Vol. 26, No. 12, Dec. 2018.
H. Hihara, A. Iwasaki, M. Hashimoto, H. Ochi, Y. Mitsuyama, H. Onodera, H. Kanbara, K. Wakabayashi, T. Sugibayashi, T. Takenaka, H. Hada, M. Tada, M. Miyamura, and T. Sakamoto, “Sensor Signal Processing Using High-Level Synthesis with a Layered Architecture,” IEEE Embedded Systems Letters, Vol. 10, No. 4, Dec. 2018.
H. Konoura, D. Alnajjar, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera, “Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-based Design and Its Irradiation Testing,” IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E97-A, no. 12, pp. 2518-2529, Dec. 2014.(電子情報通信学会 RECONF研究会 優秀リコンフィギャラブルシステム論文賞)
H. Konoura, T. Kameda, Y. Mitsuyama, M. Hashimoto, and T. Onoye, “NBTI Mitigation Method by Inputting Random Scan-In Vectors in Standby Time,” IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E97-A, no.7, pp. 1483-1491, July 2014.
H. Konoura, T. Imagawa, Y. Mitsuyama, M. Hashimoto, and T. Onoye, “Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices,” IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E97-A, no.7, pp. 1468-1482, July 2014.
R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, “Set Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects,” IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E97-A, no.7, pp. 1461-1467, July 2014.
D. Alnajjar, H. Konoura, Y. Ko, Y. Mitsuyama, M. Hashimoto, and T. Onoye, “Implementing Flexible Reliability in a Coarse-grained Reconfigurable Architecture,” IEEE Transactions on VLSI Systems, vol. 21, no. 12, pp. 2165-2178, Dec. 2013. (IEEE CASS Shikoku Chapter Best Paper Award)
R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, “Impact of NBTI-Induced Pulse-Width Modulation on Set Pulse-Width Measurement,” IEEE Transactions on Nuclear Science, vol. 60, no. 4, pp. 2630-2634, August 2013.
T. Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, “Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices,” IEICE Trans. on Information and Systems, vol. E96-D, no. 8, pp. 1624-1631, August 2013.
T. Amaki, M. Hashimoto, Y. Mitsuyama, and T. Onoye, “A Worst-Case-Aware Design Methodology for Noise-Tolerant Oscillator-Based True Random Number Generator with Stochastic Behavior Modeling,” IEEE Transactions on Information Forensics and Security, vol. 8, no. 8, pp. 1331-1342, August 2013.
D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, “Pvt-Induced Timing Error Detection Through Replica Circuits and Time Redundancy in Reconfigurable Devices,” IEICE Electronics Express (ELEX), vol. 10, no. 5, April 2013.
H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, “Adaptive Performance Compensation with In-Situ Timing Error Predictive Sensors for Subthreshold Circuits,” IEEE Transactions on VLSI Systems, vol. 20, no. 2, pp.333-343, Feb. 2012.
H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, “Stress Probability Computation for Estimating NBTI-Induced Delay Degradation,” IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol.E94-A, no.12, pp.2545-2553, Dec. 2011.
H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, “Neutron-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM,” IEEE Transactions on Nuclear Science, vol. 58, no. 4, pp. 2097-2102, Aug. 2011.
国際会議等採択論文
T. Tanaka, I. Ikeno, R. Tsuruoka, T. Kuchiba, W. Liao, and Y. Mitsuyama, “Development of Autonomous Driving System using Programmable SoCs,” in Proc. International Conference on Field-Programmable Technology (FPT 2019), pp. 453-456, Dec. 2019.
Y. Mitsuyama, T. Asada, M. Eguchi, “Measurement of Performance Variation of FPGAs under Various Operating Conditions,” in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2018), pp. 129-132, July. 2018.
T. Asada, M. Eguchi, and Y. Mitsuyama, “Performance Variation Measurement on Commercial FPGAs under Various Operating Conditions,” in IEEE Region 10 Conference (TENCON2016), (to appear).
K. Yamamoto, T. Morioka, T. Inoue, M. Mori, and Y. Mitsuyama, “Performance Evaluation Platform for Programmable Interconnect Architecture Exploration,” in Proc. 20th Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2016), pp.125–128, Oct. 2016.
J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, R. Doi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, and M. Hashimoto, “A Highly-Dense Mixed Grained Reconfigurable Architecture with Overlay Crossbar Interconnect Using Via-Switch,” in Proc. International Conference on Field Programmable Logic and Applications (FPL 2016), Aug. 2016.
R. Doi, J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, and M. Hashimoto, “Highly-Dense Mixed Grained Reconfigurable Architecture with Via-Switch,” ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 2016.
J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, R. Doi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, M. Hashimoto, “Highly-dense Mixed Grained Recon gurable Architecture with Via-switch,” in Proc. IEEE/ACM Design Automation Conference (DAC 2016) Work-in-Progress (WIP) session, 100.2, June 2016.
M. Hashimoto, D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, T. Onoye, and H. Onodera, “Reliability-Configurable Mixed-Grained Reconfigurable Array Compatible with High-Level Synthesis,” in Proc. Asia and South Pacific Design Automation Conference (ASP-DAC 2015), pp. 14-15, Jan. 2015.
Y. Mitsuyama, H. Onodera, “Variability and Soft-error Resilience in Dependable VLSI Platform,” in Proc. Asian Test Symposium (ATS 2014), pp.45-50, Nov. 2014, (Invited).
H. Konoura, D. Alnajjar, Y. Mitsuyama, H. Ochi, T. Imagawa, S. Noda, K. Wakabayashi, M. Hashimoto, and T. Onoye, “Mixed-Grained Reconfigurable Architecture Supporting Flexible Reliability and C-Based Design,” in Proc. International Conference on ReConFigurable Computing and FPGAs (ReConFig 2013), Dec. 2013.
D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, S. Noda, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera, “Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-To-Array Mapping and Its Radiation Testing,” in Proc. IEEE Asian Solid-State Circuits Conference (A-SSCC 2013), pp. 313-316, Nov. 2013.
D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, “A Comparative Study on Static Voltage Over-Scaling and Dynamic Voltage Variation Tolerance with Replica Circuits and Time Redundancy in Reconfigurable Devices,” in Proc. International Conference on ReConFigurable Computing and FPGAs (ReConFig 2012), Dec. 2012.
R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, “Impact of NBTI-Induced Pulse-Width Modulation on Set Pulse-Width Measurement,” in Proc. European Conference on Radiation and Its Effects on Components and Systems (RADECS 2012), Sept. 2012.
T. Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, “A Predictive Delay Fault Avoidance Scheme for Coarse-Grained Reconfigurable Architecture,” in Proc. International Conference on Field Programmable Logic and Applications (FPL 2012), Aug. 2012.
R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, “SET Pulse-Width Measurement Eliminating Pulse-Width Modulation and Within-Die Process Variation Effects,” in Proc. International Reliability Physics Symposium (IRPS 2012), pp. SE1.1-SE1.6, April 2012.
T. Kameda, H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, “NBTI Mitigation by Giving Random Scan-In Vectors during Standby Mode,” in Proc. International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS 2011), pp.152-161, Sept. 2011.
H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, “Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architecture,” in Proc. International Conference on Field Programmable Logic and Applications (FPL 2011), pp.189-194, Sept. 2011.
R. Harada, Y. Mitsuyama, M. Hashimoto, T. Onoye, “Neutron Induced Single Event Multiple Transients With Voltage Scaling and Body Biasing,” in Proc. International Reliability Physics Symposium (IRPS), pp. 253-257, April 2011.